Random service scanning system



G. F. ABBOTT, JR., ET AL 2,853,555

RANDOM SERVICE SCANNING SYSTEM sept. 23, 195s Filed Dec.

l2 Sheets-Sheet 1 Nk 0 RAM QW Pi Divi @ISL A GE v QQ QKIQQ QL.

G. F. ABBOTTJR A.E.J0EL,JR

' ATTORNEY swt. 23, 195s G. F. ABBoT-r, JR., ET AL l 2,853,555 RANDOM SERVICE SCANNING SYSTEM l2 Sheets-Sheet 2 Filed Deo. 28', 1955 D Il ma W QQQN QQ WN A .5. Jog/wav Bv KMX N @Fi A 7` TORNE V Sept. 23, 1958 K v G''ls'oT-r, JR., ETAL 2,353,555

'K RANDOM SERVICE SCANNING SYSTEM ATTORNEY Sept. 23, 1958 G.- F. ABBOTT, JR., ErAL 2,353,555

' RANDOM SERVICE SCANNING SYSTEM l l I ATTORNEY Sept. 23, 1958 Filed Dec. 28, 1955 G. F. ABBOTT, JR., ETAL 2,853,555

RANDOM SERVICE scANNING SYSTEM 12 Sheets-Sheet 5 COUNTER STAGE COUNTER STAGE COUNTER STAGE R/NG COUNTER C/RCU/T ATTORNEY 2 STGE COUNTER Sept. 23, 1958 G. F. ABBOTT, JR., ETAL 2,853,555

RANDoM SERVICE scANNING SYSTEM 12 Sheets-Sheet 6 Filed Deo. 28, 1955 ATTORNEY Sept. 23, 1958 G. F. ABBOTT, JR., ETAL N 2,853,555

v RANDOM SERVICE SCANNING SYSTEM Filed Dec. 28, 1955 12 Sheets-Sheet 7 FIG. 7

c. F. Aorz JR. A. E. Jong/i.

ATTORNEY IN VEN TORS Sept. 23, 1958 G. F. ABBo'rT, JR., ETAL 2,853,555

RANDOM SERVICE SCANNING SIYSTEM 12 Sheets-Sheet 8 Filed Decv. 28, 1955 G. FABBOTZJR. A .5. Job-,JR.

/NVENTORS w05 NUQ AT Tok/ver Sept. Z3, 1958 G. F. ABBOTT, JR., ETAL 2,853,555

RANDOM SERVICE SCANNING SYSTEM 12 sheets-sheet 9 Filed Dec. 28, 1955 I ATTORNEY Sept. 23, 1958 G. F. ABBOTT, JR., ETAL 2,853,555

RANDOM SERVICE SCANNING SYSTEM l2 Sheets-Sheet lO Filed Dec. 28,` 1955 TT JR. ,Jh

. uw v NQS llom o I Il m o 1 S el Qho SS Q Sl ESQ tu: Qlmf SESSJM F new X 5 N f E @m32 QQ 95m ATTORNEY Sept. 23, 1958 G.. F. ABBOTT, JR., TAL

RANDOM SERVICE SCANNING SYSTEM Filed Dec. 28, 1955 12 Sheets-Sheet 11 ATTORNEY Sept. 2,3, 1958 G. F. ABBOTT, JR., ETAL. 2,853,555

` RANDOM SERVICE scANNING SYSTEM 12 'sheets-sheet 12 Filed Deo. 28, 1955 ATTORNEY United States Patent RANDOM SERVICE SCANNING SYSTEM George F. Abbott, Jr., New York, N. Y., and Amos E.

Joel, Jr., South Orange, N. J., assignors to Bell Telephone Laboratories, lncorporated, New York, N. Y., a corporation of New York Application December 28, 1955, Serial No. 555,947

14 Claims. (Cl. 179-18) This invention relates to a line scanning system for signaling the service condition of a number of subscriber lines connected by a remote line concentrator to a central ofce.

In the Patent 2,812,385, issued on November 5, 1957, to Joel-Krom-Posin, there is disclosed a concentrator telephone system which includes remotely located line concentrators for providing connections between a large plurality of subscriber lines and a small plurality of talking trunks. The trunks -connect the line concentrators with the central office. The line concentrator system effects considerable saving in the cost of operation of the telephone plant by avoiding the necessity of providing a separate direct connection from the central olice to each subscriber line. As the central office is not directly in information communication with the subscriber lines due to the interposition of the remote line concentrator, provision is necessary for informing the central oftlce of the service condition of each of the subscriber lines as needed. The line service conditions to be determined are essentially the idle condition, in which there is no connection through a line concentrator to the central oflice, the rbusy condition, in which there is such a connection, and the service request condition in which the subscriber line is in a calling condition but not connected through the line concentrator to the central oice.

In non-concentrator telephone systems the subscriber lines terminate directly in the central oflce, and contacts on the line and cut-off relays are utilized to determine which of the line conditons exist. Such line and cut-off relays are eliminated in line concentrator systems by the provision of means for scanning the subscriber lines connected to the remote concentrator and then signaling over a common signaling path to the central ofice an indication of the service condition of each line.

In the patent application Serial No. 555,916, led on even date herewith, by M. L. Almquist, Ir., A. E. Joel, Ir., and M. Posin, there is disclosed a line scanning system for remote line concentrators. A scanner pulse generator in the central oice supplies a series of readying pulses and a series of scanning pulses through a control circuit and over control paths connecting the line concentrator with the central oice. The readying pulses successively condition groups of scanning units which are individually associated with the subscriber lines. The scanning pulses are applied successively to groups of scanning units, each of which includes one unit in a readied group of units. During a complete scanning cycle the total number of scanning pulses is equal to the number of subscriber lines since each scanning pulse is applied to one scanning unit. Depending upon the condition of a subscriber line, the scanning pulse corresponding thereto is either blocked or transmitted to the central oce as a service request or line busy indication.

When a call is ibeing served, the central oice control circuit stops the scanning cycle so that the readying and V scanning pulses are not sent over the control paths tothe line concentrator. In such scanning systems, when the call has been served, the control circuit restarts the scanning cycle. If more than one line is requesting service when the scanning cycle is restarted, they are served in the numerical order of their positions in the scanning cycle. The line which is scanned earlier in the cycle is always served rst.

lt is an object of the present invention to avoid the preferential service given to lines scanned early in the cycle, and to avoid service breakdown due to trouble developing in equipment associated with such lines.

In one specific illustrative embodiment of the present invention a free running pulse source in the central oice control circuit supplies random pulses which are not synchronized to the time base of the scanning cycle. When a service request indication is received at the central ofce, an originating register registers the identity of a scanned line requesting service, and the scanning cycle is halted. After the service requesting line is connected to a talking trunk at the line concentrator, the central oce control circuit restarts the scanning cycle. Under control of the random pulse source, however, the originating register is made insensitive to service request indications for a portion of the scanning cycle following each call. The originating register is readied, or becomes sensitive to service requests, when a pulse is supplied by the random supply. Scanning is in this manner effectively resumed at a random or different point in the scanning cycle after each call is served.

If the interval between the random pulses is larger than, or equal to, the scanning cycle duration, the originating register may not become sensitive to a service request indication during the rst cycle after scanning is resumed. Such a delay is, of course, to be avoided. If the interval between the random pulses is much smaller than the scanning cycle duration, the subscriber lines scanned during this interval are always preferred over those scanned later during the scanning cycle. A feature, therefore, of the present invention relates to pulse supply means which provides random pulses spaced at an interval that is slightly smaller than the scanning cycle duration.

Further objects and features will become apparent from the following description and accompanying drawings wherein:

Figs. 1 through 1l, when arranged in accordance with Fig. 12, provide a circuit representation of the line concentrator random scanning system of the present invention, wherein:

Fig. 1 illustrates a plurality of line concentrator amplifiers;

Fig. 2 illustrates a plurality of subscriber lines and line concentrator scanning units;

Figs. 3 and 5 illustrate the line concentrator ring counter circuit;

Fig. 4 illustrates the connections between the line concentrator and the central oiiice;

Figs. 6, 7 and 9 illustrate various circuit components in the scanning control circuit at the central oce;

Fig. 8 illustrates diagrammatically the central oice trunk switching system and random pulse generator; and

Figs. 10 and ll illustrate the ring counter register circuit at the central oiiice;

Fig. l2 illustrates the arrangement of Figs. 1 through ll; and

Fig. 13 is a series of pulse'time curves illustrating the operation of the scanning -system of the present invention.

In the drawing, the relay contacts are shown detached from the relay windings. The first digit of each reference number indicates the gure in which it appears and A the letters indicate the function thereof. Relay 3FG, for

example, is thel vertical file relay zero and appears in Fig. 3. The designation ofthe contact of a relay includes in parentheses the relay reference number with the. first digit before the parentheses indicating the figure in which the contactappears. Contact (3F0'), for example, appears in Fig. 5 and is a contact of the vertical le'relay zero which appears in Fig. 3. Contacts which are closed whenthe relay is operated are represented by an X crossing the lines representing the connecting conductors.

Referring to Figs. 1 through 11when arranged in accordance with Fig. 12, the line concentrator shown in Figs. 1 through 5 situated atl a location remote from the central office shown in Figs. 6 through 1l, and has connected thereto 60 subscriber stations 2800-59 by the subscriber lines v2L00-59. The effect of utilizing line concentrators is, as described in the above-identified disclosure by Joel-Krom-Posin, to place a part of the switching equipment of the central oflice at a distance therefrom'to conserve outside plant facilities. The line con. centrator is connected to the central ofce by a plurality of trunks, only one of which, trunk 4T, is shown, and by three control pairs 4CPO-2. The trunks 4Tt provide a talking path between the line concentrator and the central oce and the three control pairs 4CPO-2 provide fory signaling paths to and from the central oiice control equipment.

With all the subscribery lines 2L00-59 idle, the central oice continuously scans the 60 subscriber lines 2L00-S9 which are connected to the line concentrator. tral oice provides to the concentrator, as shown in the pulse sequence diagram of Fig. 13, twelve -volt vertitical group pulses spaced from each other at intervals of 10 milliseconds and ve 15-volt vertical iile pulses spaced from each other at intervals of 2 milliseconds between each two consecutive vertical group pulses. The vertical file and vertical group pulses are half millisecond pulses and the complete cycle has a duration of 120 milliseconds. Scanning pulses 4for the line concentrator are provided from a scanner pulse source or generator 7PS. Such generators are described, for example, in the above-identified disclosure by Ioel-Krom-Posin. The pulse source 7PS includes a kilocycle oscillator, not shown, which generates the various pulses. In addition to the vertical group and vertical le pulses, as shown in the pulse sequence diagram in Fig. 13, the source 7PS supplies one reset pulse at the beginning of the cycle to insure that the operation of the line concentrator scanning cycle isy synchronized ,with the pulse source 7PS. The reset pulse also functions as the first verticalle pulse so that only 59 vertical lile pulses, as sucha1e provided instead of 60. During one scanning cycle the pulse source 7PS therefore supplies one reset pulse, twelve vertical group pulses and 59 vertical file pulses; one vertical le pulse, if the reset pulse is included, foreach of the subscriber lines 2L00-59 connected to the line concentrator.

The pulse source 7PS supplies pulses from terminals 1 through 7 as follows:

(1) Terminal 1 is for the serially arranged vertical tile pulses;

(2) Terminal 2 is for the serially arranged vertical groupvpulses;

(3) Terminal 3 is `for the reset pulses;

(4) Terminal 4 is for mark pulses which are hereinafter described;

(5) Terminal S is connected through the controllead 8L4 to theswitching circuit 800 which is also hereinafter described;

(6) Terminal 6 indicates five terminals for individually and cyclically providing Vertical file pulses; and

(7) Terminal 7 is for timingrpulseseach of which occurs in time between two consecutive vertical file pulses. There are timing pulses in a 120-millisecond cycle.-

The cent As shown in the sequence diagram, the vertical group pulses are in phase with the timing pulses, and the reset pulses are in phase with the vertical tile pulses.

The pulse source 7PS supplies the reset, vertical file and vertical group pulses to two synchronously operated ring counter circuits; one in the line concentrator and the other in the central oice. The central oflice ring counter circuit 1000, which functions, as is hereinafter described, to register the identity of a calling subscriber, is shown in Figs. 10 and 11 and the line concentrator ring counter circuit 500 is shown in Figs. 3 and 5. The circuits 1000 and 500 are similar and include, respectively, the vertical group ring counters 11VGR and SVG and the vertical tile ring counters IOVFR and 3VF.

The source 7PS supplies vertical file pulses to the counter 10VFR from terminal 1 through the inhibiting gate 9VFR, and vertical group pulses to the counter llVGR from terminal 2 through the inhibitingV gate 9VGR. The gates 9VFR and 9VGR are similar. with each having three terminals designated 1-3. The termif nal 1 is the output terminal, the terminal 2 is the input pulse terminal and the terminal 3 is the control input terminal. With -20 volts at its control terminal 3, the gate 9VFR` functions to allow passage of pulses from the input terminal 2 through to the output terminal 1. The ,--20 volt potential at terminal 3 forward-biases the varistor 9V1 which is connected thereto through the resistor 9R1. The varistor 9V1 is connected to the terminal 1 and through the capacitor 9C1 to terminal 2, and the junction between capacitor 9C1 and varistor 9V1 is connected through the 4resistor 9R2 to the -20 volt battery 9B1. The presence of a positive 15-volt pulse from the source 7PS causes the potential at the junction between the capacitor 9C1 and the varistor 9V1 to increase to -5 volts which is 15 volts positive with respect to the potential at terminal 1. The forward-biased varis tor 9V1'allows the pulse through to appear across the load resistor 9R1. In its inhibiting state the terminal 3 is at a potential of -2 volts and the varistor 9V1 is reversed-biased with a potential of approximately 18 volts. The presence of a positive 15-.volt pulse across the input resistor 9R2 is insuicient to overcome the reverse biasing of varistor 9V1 sothat an output pulse does not appear across the resistor 9K1. Terminal 3 of the gate 9VFR, and terminal 3 of the gate 9VGR as well, are connected tothe ip-op circuit 9RH which provides, as is hereinafter described, the 2O volt normal potential and the '-2 volt inhibiting potential.

The vertical le and vertical group pulses from the pulse source 7PS are supplied in this manner through the'gates 9VFR and 9VGR, respectively, to the counters 10VFR and 11VGR in circuit 1000, with ve pulses being supplied to the counter 10i/.FR for each pulse being supplied to the counter HVGR.

The counter 10VFR is a five-stage ring counter having stages l10VFR0-4 and the counter llVGR is a twelvestage ring counter having stages 11VGRO-11. A ring counter may be referred to as a walking circuit or a sequence-circuit which advances one step for each input pulse supplied thereto. The vertical le pulses from the pulse source 7PS through gate SBK/'FR are supplied to the input terminal 3 of each of the ve stages 10VFRO-4. A single counter stage, such as thestage itVFRt), may be thought of as a combination of an `enabling gate and flip-flopfcircuit. A stage is said to be gated when its gate is enabled, and is said to be on when its pfop circuit is set. A stage may be turned on only if its gate is enabled to allow the Ainput pulse through to set or turn ont-its flip-hop circuit. When a stage is turned on the potential at its output terminal 2 changes from -20 volts to -2 volts to enable the gate of the succeeding stage. Assume for example that at the beginning of the scanning cycle the stage 10VFRO has its flip-iiop circuit set. Only one of the stages 10VFRO-4 is set at a time and the stage succeeding the set stage is the only gated or enabled stage. The input terminal 3 through which they positive pulse is supplied is connected through the input coupling.-

capacitor C1 and the varistor 10D3` to the emitter electrode of the transistor 10T1. The transistor 10T1 is Aone of two junction type transistors 10T1 and 10T2 which are connected in a hook circuit to functon'together as a contact type transistor. Such hook circuits are described', for example, in the Patent 2,655,609 which issued to W. Shockley on October 13, 1953. The emitter electrode of transistor 10T1 is connected to ground through the resistor 10R1 and through the varistor 10D2. The resistor 10R1 functions as a load resistor for the input pulse and the varistor 10D2 provides a low resistance path for the emitter sustaining current and also functions to dissipate any negative pulses to ground. The base of transistor 10T1 is connected to the collector of transistor 10T2, to to the |5 volt direct-current potential source 10131 through the base resistor 10R4 and through the reset'terminal 4 to the terminal 5 of the succeeding stage 10VFR1. The emitter electrode of transistor 10T2 is connected to the output terminal 2 and to the -20 volt battery 10B2 through the resistor 10R6.

With the first stage 10VFRO on, the output terminal 2 thereof is at a potential of -2 volts due to the current through the resistor 10R6. With the -2 volt potential at terminal 2 of stage 10VFRO, the varistor 10D3 of stage 10VFR1 the varistor 10D3 of stage 10VFR1 is essentially forward-biased. The terminal 2 of stage 10VFRO is connected through the terminal 1 of stage 10V FRI and resistor 10R3 to the varistor 10D3. With the varistor 10D3 in stage 10VFR1 forward-biased the stage 10VFR1 is `enabled so that an input pulse through terminal 3 thereof causes it to turn on. lf stage 10VFRO is not on and its terminal 2 is at a potential of -20 volts, varistor 10D3 in stage 10VFR1 is reversed-biased so that an input pulse through its terminal 3 is not effective to turn it'on.

When the first vertical file pulse' is supplied to the terminals 3 of stages 10VFRO-4 from theV source 7PS, it turns on the stage lllVFRl through its enabled gate circuit which includes the forward-biased varistor 10D3. The potential at terminal 2 of stage 10VFR1 changes from -20 volts to -2 volts to enable the stage lflVFRZ and reset the stage lflVFRf. The terminal 2 in stage 10VFR1 is connected through the capacitor MC2 of stage 10VFR1, varistor 10D4 and terminal 5 to terminal 4 of stage ISBVFR and terminal 4 is connected, as described above, to the base electrode of transistor 10T1. When terminal 2 of stage 10VFR1 changes in potential from -20 volts to 2 volts, the change in potential is provided to the base of transistor 10T 1 in stage 10VFRO causing the stage 10VFRO to turn off. When the stage 10VFRO is turned off, in this manner, the potential at its terminal 2 decreases from -2 volts to -20 volts, disabling the gate circuit including the varistor 10D?, in the stage 10VFR1.

To briefly recapitulate, the first pulse supplied. to terminals 3 of stages tVFRfl-l turns on the stage l'VFRl which enables the stage 10X/Flu and resets or turns ofiC the stage 10VFRO. When they stage 10VFRO is turned off it disables the stage 10VFR1. After the first pulse, therefore, the stage 10VFR1 is the only stage that is on and the stage 10VFR2 is the only stage that is enabled.

The second positive pulse from source 7PS' turns on the stage 10VFR2 which enables the stage 10VFR3 and turns off the stage 10VFR1 which in turn disables the stage 10VFR2. The pulses supplied to the terminals 3 of the stages 10VFRO-4 in this manner advance the setting from stage to stage with the sixth pulse being equivalent to pulse No. l. The sixth 'pulse is equivalent to the first pulse because ythe stages 10VPRO-4 are connected in a ring with the output terminal 2 of stage 10VFR4 being connected to terminal 1 of stage IOVFRG and the terminal 5 of stage 10VFR4 being connected to the reset terminal 4 of stage 10VFRO. The above. sequence continues: from stage to stage in the counter 10VFR until the. input pulses are removed. A similar sequencev ofv events takes place in the counter llVGR except that it takes twelve pulses to complete a cycle instead of five.

At the beginning `of each cycle a positive reset pulse is supplied from terminal 3 of the pulse source 7PS through the inhibiting gate 9RRG, the amplifier 9RR and capacitor 9C6 to the register counter circuit 1000. The gate 9RRG, as Well as all the inhibiting gates hereinafter referred to, is similar to the gate 9VFR described abo-ve, and the reset amplifier 9RR is similar to the amplifier GVFL, which is hereinafter described in detail. The capacitor 9C6 is connected to ground through the resistor 9R7 and through lthe reverse-biased varistor 9V8 to the hereinafter described delay circuit 9RLD2. The reset pulse through the amplifier 9RR is supplied, respectively, through the serially connected varistor 10D1 and resistor 10R to the terminal 1 of stage 10VFRO, and through the serially connected varistor 10D1 and resistor 10K to the terminal 1 of stage 10VFRO, and through the serially connected varistor 11D1 and resistor 11R to the terminal 1 of the stage 11VGRO to turn these stages on. The resetpulse is also supplied respectively through the varistors 10D7 and 11D7 to the reset terminals 4 of the other stages in the counters 10VFR and llVGR to reset or turn off these stages. At the beginning of each cycle,

therefore, the pulse source 7PS supplies a reset pulse to the counters 10VFR and 11VGR to return them to normal with only stages 10VFRO and 11VGRO set. The source 7PS does not supply a vertical file pulse when the reset pulse is supplied. The reset pulse functions as the rst vertical file pulse since it is supplied to the input terminals 1 of stages 11VFRO and 11VGRO. The source 7PS therefore supplies twelve vertical group pulses, onel reset pulse and 59, not 60, vertical le pulses to the regis` ter circuit 1000.

The pulse source 7PS supplies the vertical le, vertical group and reset pulses to the counters 10VFR and lVGR as described above, and also through the control leads 4CP1 and 4CPZ to the concentrator. Terminal 1 of the pulse source-7PS is connected through the capacitor 6C5A and the varistor 6V2, shunted by the resistor 6K8, to the terminal 2 of the inhibiting gate 6VFS which is similar, as described above, to the gate 9VFR. With the inhibiting gate GVFS open the vertical file pulses from the pulse' source 7PS are supplied through the capacitor 6C1 and' amplifier 6VFL to the transformer 4T2.

The amplifier 6VFL, which is a transistor pulse amplifier having transistors 6T1 and 6T2 connected in a hook arrangement, functions to transform the pulses supplied from the source 7PS into square wave pulses of 15-volt' amplitude and SOO-microsecond duration, The illustrative embodiment of the present invention includes two l types of amplifiers; a single input SOO-microsecond pulse transmitting amplier and a double input -microsec by an input pulse but returns to its original quiescent con-v dition due to the internal circuit action. This is due to the fact that the potential on the emitter of transistor 6T2 returns to a predetermined negative biasing potential, with respect to the base due to a biasing path from batteryv 6B1 through resistors 6K5 and 6R41, varistor 6V1, shunted by resistor 6R1, and the resistor 6K2 to battery 6B2. In.

its normal state the emitter electrode of transistor 6T2 is at a potential of 3.2 volts while the base` thereof is Vat a potential yof 4.42 volts. Thus an input pulse which is: only just over 1.2 volts through terminal 1 and capacitor. 6C2-from the pulse-Source 7PS causesthe amplifier to trigger. The capacitor 6C3, which is connected between4 resistors 6R4 and 6K5, controls the duration of the output pulse supplied from the emitter of transistor'TI through terminal 2 ofthe amplifier 6VFL, The input pulse', through terminal I, triggers the amplifier SVFL p rovidlng a charging path from the battery 6BI on one side of capacitor 6C3 and through varistor GVI and transistors 6T2 and 6T1 and resistor 6K3 to battery 6B2 on the other side of capacitor 6C3. After the capacitor 6C3 has charged, it offers a high impedance path to the +5 volt battery 6BI allowing the biasing path, described above, to function, as the capacitor 6C3 discharges allowing the amplifier 6VFL to return to normal.

The output pulse of amplifier 6VFL is connected from the output terminal 2 thereof through the resistor Re to the upper primary of transformer 4T2. 'The serially connected resistor 4R13 and upper primary of transformer 4'1`2 are shunted by the varistor SVI which is connected to battery 4BI. The positive l5-volt pulse from amplifier 6VFL is supplied, in this manner, through the transformer 4T1 and the control leads 4CPI to the line concentrator.

In a similar manner, the vertical group pulses are supplied from terminal 2 of the pulse source 7PS to the counter IIVGR, as described above, and through the inhibiting gate 7VGSZ, resistor 7R1, the inhibiting gate 7VGSI, amplifier 7VGL, transformer 4T3 and control pair or leads 4CP2 to the line concentrator. The path from amplifier '7VGL, which is similar to the amplifier 6VFL, is through resistor iRt, and the upper primary of transformer 4T3 to battery 4B2. The resistor 4K6 and the upper primary of transformer 4T3 are shunted by the varistor 4V3.

The pulse source 7PS also supplies, as described above, a reset pulse instead of the first vertical file pulse to the line concentrator. The reset pulse is supplied from terminal 3 of the pulse source 7PS through the inhibiting gate 7RS2, the inhibiting gate 7RSI, the capacitor 7C1, the amplifier 7RL, which is also similar to amplifier 6VFL, and resistor 4K7 to the lower primary winding of trans' former 4T3 which is connected to the battery 4B2. The resistor 4R7 and the lower primary winding of transformer 4T3 are shunted by the varistor 4VS. In this manner the vertical file pulses are supplied from the central ofiice over the control pair 4CP1 and the vertical group and reset pulses are supplied over the control pair e' formers 4T4-6. The upper primary of the transformer "t" 4T5, which is shunted by the resistor 4R10, is connected to the input terminals I and 3 of the vertical file receiving type amplifier IVF; the upper primary winding of the transformer 4T6, which is shunted by the resistor 4R11,

is connected to the input terminals I and 3 of the vertical f group amplifier IVG; and the lower primary winding of the transformer 4T6 is connected to the input terminals 1 and 3 of the reset amplifier IRS. The amplifiers IRS, IVF and IVG are all receiving type amplifiers and amplify the respective signals supplied thereto from the central office.

The amplifier IVF, which is shown in detail, is substantially similar to the amplifier 6VFL described above. The vertical file pulses through the control leads 4CPI, however, are connected through the two input terminals I and 3, instead of one, to the circuitvcomponents therein. The terminals I and 3 are connected across the capacitor 1C4 and to the emitter electrode of transistor ITZ respectively through the resistor IR6 and the varistor IVI. The'input to the amplifier 6VFL is a single terminal input, as described above, whereas the input to the amplifier IVF is, in this manner, a double terminal input. When an input pulse is provided to the amplifier IVF, terminal I becomes positive with respect to terminal 3 causing the trigger circuit including the transstors ITI and 1T2 to trigger. The capacitor 1C4 functions as a filter to prevent triggering amplifier IMK, which is also connected to transformer 4TS, when transistor ITI and 1T2 become conductive. When the transistors ITI andk 1T2 in amplifier IVF become conductive the emitter potential of transistor ITZ decreases. Without the filter capacitor 1C4, a negative pulse would be supplied to the upper primary of transformer 4TS to initiate a positive pulse in the lower primary thereof. Capacitor IC4 is provided therefor to prevent such interaction and the false operation of amplifier IMK resulting therefrom. The emitter electrodes of transistors ITI and 1T2 are connected by a feedback capacitor ICS which makes the amplifier very sensitive. The amplifier IVF provides a pulse of shorter duratio-n than that provided from the amplifier 6VFL due to the utilization of a small base capacitor' 1C3. The emitter electrode of transistor ITI is connected to the output terminal 2 through the varistor IV2 which is connected to the battery IB2 through the resistor IR7. The resistor IR7 and the varistor IV2. function as an isolating circuit component between the amplifier IVF and the ring counter 3VF. The isolating varistor IVZ is necessary to avoid false triggering through capacitor ICS due to noise or other disturbances. The other circuit components in amplifier IVF are similar to the corresponding ones in amplifier 6VFL.

The amplified vertical file pulses are supplied fromv the output terminal 2 of amplifier IVF to the five-stage vertical file ring counter SVF which is similar to the counter IVFR described above. The vertical group pulses received by the vertical group amplifier IVG are supplied from the output terminal 2 thereof to the vertical group ring counter SVG which is similar to the vertical group counter IIVGR described above. The counters 3VF and SVG are, in this manner, stepped by the vertical group and Avertical file pulses in synchronism with the counters 10VFR and IIVGR.

The reset pulse, amplified through the amplifier IRS, is supplied from the output terminal Zthereof through the capacitor IRSC of the network 1G, lead ILI and the varistors 3D7 and SD7, respectively, to the reset terminals 4 of the stages 3VFI-4 and SVGI-II. The reset pulse is also. supplied from capacitor IRSC through the varistors SDI and 3D1, respectively, to the terminals 6 of stages 3VFO and SVGG. The application of the vertical file, vertical group and reset pulses to the counters SVG and 3VF is, in this manner, similar to the application of these pulses to the counters IIVG and IGVF, described above. As long as there are no service requests from any of the subscriber lines ZUM-59 or terminating calls thereto, the two circuits 100) and Stift or the two sets of counters, one in the central ofiice and one in the line concentrator, synchronously step through the count of 60 with a reset pulse being supplied at the beginning of each cycle to insure the synchronism of the two sets of counters.

Capacitor IRS of network IG is also connected to the reset terminal 3 of the ip-fiop circuit IM which is similar to the hereinafter described flip-flop circuit SHGT. The resistor IRSI which is also connected to capacitor IRSC provides a recharge path for the capacitor IRSC to ground.

At each combination of operated counter stages SVG@- 11 and 3VFO-4 a pulse is directed to scan one of the 60 lines 2L00-S9 by the line scanning units 21800-59. The units 2LS00-S9 connect the counters SVG and 3VF to the lines 2L00-59. Each of the line scanning units 2LSOtl-S9 has two gating circuit components, one controlled by the counters 3VF and SVG and the other controlled by the condition of the associated line. The first gating circuit component which includes the varistor 2D functions as an enabling or readying'component for the scanning unit.

The ring counter SVG functions to successively ready groups of Afive horizontally arranged line vscanner units ata time by changing the reverse-bias across varistor 2D from -20 volts to -32 volts. When the stage 5VGO, for example, is set, a positive pulse is provided from the output terminal 2 thereof through resistor 2VG of the line scanner units 2LSO0-4 to the respective varistors 2D therein. The ve varistors 2D in the units 2LS00-4 become biased to allow the passage of pulses from the ring counter 3VF through capacitors ZVF. The varistors 2D in the other 55 units 21505-59 are reversedbiased by the `-20 volt potential at terminals 2 of stages VG1-11. The ring counter SVF provides scanning pulses successively to twelve line scanning units at a time. When stage 3VFO, for example, is set, a positive pulse is provided from the terminal 2 thereof to the capacitors ZVF inthe units 2LS00, 2LS05, 21510, 214315, 2LS20, 2LS25, 21.530, 2LS35, 2LS40, ZLS, 21.550 and 2LS55. Of these, only the unit ZLSSS, however, has been readied at this time by the ring counter SVG when 'stage SVGO is on. The positive pulse from terminal 2 of counter stage 3VFO, therefore, is connected through the capacitor 2VF of the unit 2LS00, varistor 2D and capacitor 2C to the varistor 2S. The varistor 2S is part of the second gating circuit component which is controlled by the line condition.

Each line has associated therewith a resistor 2GS which is connected from the tip of the line to the -l-S volt source 2B1 and a resistor ZES which is connected from the ring lead of the line to the I--20 volt battery 2B2 through the varistor ZV1. If the subscriber line 2804 is open, or in a receiver-on-hook condition, the battery 2B2 functions to reverse-bias the varistor 2S to inhibit the passage of the scanning pulse from 'the ring counter SVF. When, however, the subscriber line 2L06 is in a calling condition with the line closed, a circuit is completed from battery 2B1 through resistor GS, substation 2S00, resistor ZES and varistor ZV1 to battery 2B2. The potential at the junction between varistor 2S and capacitor 2C becomes sufciently positive to allow the scanning pulse from the ring counter stage EVFS to pass through the varistor 2S to the service request amplifier 1SR. The scanning units 2LS00-59 in this manner allow the vertical le pulses to pass through as a service request pulse when both gating circuit components are enabled. The first component which includes varistor 2D is enabled by the counter SVG and the second component which includes varistor 2S is enabled when the associated line is closed. When, however, the line 2L04 is connected to one of the trunks 4T, and is therefore in a busy condition the varistor 2S, as is hereinafter described, is reverse-biased.

If all the lines 2L00-59 remain idle the scanning sequence continues under control of the three sets of pulses, the vertical group, the vertical file and the reset-pulses from the central ofce. Each vertical group pulse readies five line scanning units and each vertical le pulse scans one 'of the tive readied line scanning units. In this manner the five readied line scanning units are successively scanned by the ve vertical tile pulses which occur between two of the vertical group pulses. At the time position for the rst vertical le pulse in the scanning cycle the vertical le pulse is actually omitted, as described above, and a reset pulse is transmitted from'the central ofce to insure the synchronism of the counters SVG and 3VF. The stage 3VRO, however, when reset is on and supplies a pulse to the scanning unit 2LS00.

When a call is initiated at one of the substations 2800-59 the vertical tile pulse corresponding thereto from the ring counter 3VF is transformed by the associated one of scanning units 2LS00-59 to a service request pulse and supplied through the amplifier 1SR and resistor 4R9 to the lower primary winding of transformer 4T4. The amplier 1SR is similar to the amplifier GVFL described above and has a varistor 1SRV connected to ,input terminal 1` The varistor 1SRV, which is shunted by theresistor ISRR, functions tto couple negative pulses to ground. The lower'primary winding of transformer 4T4 is connected to the varistor 4V6 and the battery 4B3 and the secondary of transformer 4T4 is connected through the .control pair 4CPO to the secondary of the transformer 4T1 in the central oice. The lower primary winding of transformer 4T1 is connected through the resistor 4R3 to the amplifier 6SRL which is similar to the amplifier IVF described above. The output of the amplifier 6SRL is connected through the inhibiting gates 6CH@ and GSRS to the iiip-iopcircuit SHGT.

The ip-op circuit SHGT is a bistable transistor trigger circuit having two Vtransistors ST1 and ST2 connected in a hook arrangement. An electrical pulse applied to the input terminal -1 triggers the circuit from one state to the other and leaves it there until a reset pulse to its terminal 3 triggers it back again to its former state. The llip-op circuit'SHGT is normal or of when its output terminal 2 is at a potential of -20 volts and offnormal or on when it has received a positive pulse through its set terminal to change the potential at its output terminal 2 to -2 volts. A positive pulse through the reset terminal 3 restores the potential at its output terminal 2 to 20 volts. The time consumed in changing the output potential from one value to another is approximately fyo of 1 microsecond.

When the flip-ilop circuit SHGT is in its off condition a very small amount of current somewhat less than 10 microamperes is supplied from the +5 volt source SB2 through resistor SR2, transistor ST1 and resistor SR1 to ground. The transistor ST1 represents almost all of the impedance in this .circuit path. With a 5-volt potential across transistor ST1 the emitter thereof is backbiased so that the transistors `ST1 and ST2 are in their low current quiescent condition. There is also a small current through a path between the source SB2 and a 20 volt source SB1. This path is from source SBZ through resistor SR2, the base-to-collector path through transistor ST1, the `base-to-emitter path of transistor ST2 in parallel with resistor SRS and with the collector-toi emitter path of transistor ST2, then through resistor SR4 to battery SBI. With transistor ST2 being in its olf or low current quiescent condition most of the potential drop is thereacross so that terminal 2 is at a potential of '20 volts.

When a positive pulse is supplied to terminal 1 of sufficient magnitude to raise the potential of the emitter electrode of transistor ST1 above that of its base electrode, the transistors ST1 and ST2 become conductive. The input terminal 1 is connected through the capacitor SC1 to the emitter electrode of transistor ST1 which is connected to ground through the resistor SR1 and also through the varistor SDS. When the transistors ST1 and ST2 are turned on, there is a low resistance path from ground through'the varistor SDS, the emitter-tocollector path through transistor ST1, the base-to-emitter path of transistorSTZ and resistor SR4 to battery SBI. The increase in current through the resistor SR4 causes an lS-volt drop across it to change the potential at terminal 2 to -2 volts. The voltage drop-across the collector-to-emitter path of transistor ST2 is very small when the transistor VST2 is on so that the collector electrode thereof is effectively at the -2 volt potential. With the emitter electrode of transistor ST1 effectively at ground potential it is therefore 2 volts more negative than its base electrode which is connected to the co1- lector of transistor ST2. This condition holds the transistors on to provide for the bistable operation. The circuit SHGT includes a varistor-SD2'which is connected from the emitter electrode of transistor ST2 to ground. The varistor SDZ prevents the output lead from going positive-ory above ground potential. i

rThe circuit SHGT remainsin this stable on condition until fa positive pulse isl received'through' the reset terminal 3. The'reset'terminal 3 is connected through thc YIl capacitor SC2 and varistor 8D1vtor the base electrode of transistor ST1. The junction between capacitor SC2 and varistor SDI is connected to ground through the resistor SRS. The positive pulse to the base electrode of transistor ST1 makesV it more positive than the emitter electrode thereof turning off the transistors ST1 and ST2.

When the ip-iiop circuit SHGT operates it functions generally to stop the transmission of the. vertical group pulses but not the vertical file pulses to the concentrator and to lock the counter circuit 1000, described above, to register the designation of the calling line. The vertical file pulses are uninterrupted so that the five lines in the vertical group which includes the line requesting service are scanned every. milliseconds. Each time the requesting line is'scanned another service request pulse is returned over the control pair 4CPO to the central oice. The successive detection of these service request pulses, as is hereinafter described, verifies the continuance of the service request. If a successive service request pulse is not detected it indicates that the service request has been abandoned..

More specifically the change from volts to -2 volts at the output terminal 2 of the flip-flop circuit SHGT performs the following functions:

(l) It opens the enabling gate 6VF which connects the reset pulses from terminal 3 of the pulse source 7PS to the vertical le signaling path to the line concentrator so that a reset pulse, if any, will now be transmitted to the line concentrator as a vertical file pulse. The gate 6VF is a three-terminal device with an input terminal 2, an output terminal 1 and a control terminal 3. Normally with 20 volts at terminal 3 the gate 6VF functions to prevent the passage of pulses from terminal 2 to terminal 1. Terminal 3 is connected to the varistor 6V3 through resistor 6R6 and Varistor 6V3 is connected to terminal 1 and to terminal 2 through capacitor 6C4. With -20 volts at terminal 3, varistor 6V3 which is also connected to ground through resistor 6R7 is reversebiased. When circuit SHGT changes the potential at terminal 3 of gate 6VF, varistor 6V3 is reverse-biased by only 2 volts so that the reset pulse from source 7PS passes through gate 6VF and thence through gate 6VFS, capacitor 6C1, amplifier 6VFL, transformer 4T2 and the control pair 4CP1 to the line concentrator.

(2) Circuit SHGT also opens the enabling gate GSRC, ".f

the p-op circuit 9RL in order to monitor for continued dial-tone request. The amplifier 6SRL, as described above, and the amplifier 9RLD1 are similar to the amplifier 6VFL, and the flip-flop circuit 9RL is similar to the circuit SHGT described above. The delay circuit 9RLD2 is a monostable amplifier having transistors 9T1 and 9T2 connected in a hook arrangement. The output terminal 2 of amplifier 9RLD1 is connected through capacitor 9C3 to the input terminal 1 of circuit 9RLD2. Terminal 1 is connected directly to the base electrode of transistor 9T1 and through the varistors 9V5 and 9V6 to the emitter electrode of transistor 9T1. The varistor 9V5 is reverse-biased by the capacitor 9C3 which is charged by the -20 volt battery in amplifier 9RLD1, and varistor 9V6 is forward-biasedby battery 9B7 which is connected thereto through resistor 9RS. Varistor 9V6 is also connected through capacitor 9C2 to battery 9136 and to terminal 1 through resistor 9R4. The positive pulse provided by the differentiating capacitor 9C3 does not trigger circuit 9RLD2 because the emitter and base potentials of transistor 9T1 become the same when varistor 9V5 is forward-biased by the positive pulse. The trailing edge of the positive pulse from amplifier 9RLD1, however, provides a negative pulse' to the base of transistor 9RLD2 causing circuit 9RLD2 to trigger. The delay provided for the second service request pulse is essentially the length of the pulse provided by amplifier 9RLD1 since the trailing edge thereof is utilized to trigger the circuit 9RLD2. Additional, though minor, delays are provided through the control leads 4CPO-2 but the additional delay provided by circuit 9RLD2 is necessary to insure the complete operation of the ip-op circuit 9RL. If the second service request pulse arrives during the triggering interval of circuit 9RL it is ineffective to reset the circuit and results in an abandonment of servicing the call. The emitter electrode of transistor 9T2 is connected to battery 9B7 through resistor 9K6 and to the output terminal 2. The second service request pulse will be provided, in this manner, from the output terminal 2 of circuit 9RLD2 to the reset terminal of the flip-Hop circuit 9RL.

(3) Circuit SHGT also closes the inhibiting gate 7VGS2 which blocks the vertical group pulsing from terminal 2 of the source 7PS to the line concentrator.

(4) Circuit SHGT also closes the inhibiting gate 9RRG to block the pulse source 7PS from resetting the t ring counter 1000.4

(5) Circuit SHGT also closes the inhibiting gate 7RS2 to block the transmission of the reset pulses to the line concentrator as reset pulses.

(6) Circuit SHGT also causes the operation of the horizontal group relay SHG which is also connected to battery SB3.

(7) Circuit SHGT also closes the inhibiting gate SRRN over a control path through varistor 9D1 to block the supply of random pulses from the random pulse generator SPG. The generator SPG supplies S-millisecond l5-volt positive pulses spaced at an interval which is slightly smaller than the scanning cycle interval. In the illustrative embodiment disclosed herein the scanning cycle has a l20millisecond duration. It is desirable to have the interval between pulses from the free-running, or random generator, less than the l20millisecond scan cycle so that the system becomes sensitive to service requests within the next complete scanning cycle after service of an originating call.

(8) Finally, circuit SHGT also sets the ip-op circuit 9RH, and closes the gate 9RH1. The inhibiting gate 9RH1 provides a connection from the timing pulse terminal 7 of source 7PS to the reset terminal of dip-flop circuit 9RH, Circuit 9RH is in this manner maintained in its normal condition. When the gate 9RH1 is closed the timing pulses are not supplied to reset circuit 9RH.

When the flip-flop circuit 9RH is set it performs a number of functions:

(l) It closes the inhibiting gates 9VGR and 9VFR to disconnect counter 1000 from source 7PS and locks the counter 1000 to register the identity of the calling line.

(2) It closes the inhibiting gate 6SRS over a control path through varistor 9D3. Terminal 3 of gate 6SRS is connected to the -20 volt battery 6B5 through resistor 6R11. Gate 6SRS opens the input lead to the liip-op circuit SHGT which, however, remains set until a reset pulse is applied to terminal 3 thereof. As hereinafter described the inhibiting gate 6SRS remains closed after the central office is normal and ready to accept other service requests until a random interval has elapsed.

(3) It applies a control potential through varistor 9D2 to the already closed inhibiting gate SRRN. As described above gate SRRN was closed when the flipflop circuit SHGT operated. The control terminal 3 of gate SRRN is connected to the -20 volt battery SBS through resistor SRS which normally maintains gate SRRN open.

l(4) It opens the enabling gate 9RNS to connect the next timing pulse from terminal 7 of source 7PS to the input terminal 1 of the flip-op circuit lSRNS. The next timing pulse sets the flip-flop circuit SRNS which provides 'an additional control potential through varistor 8D4 to the already closed inhibiting gate 6SRS. Gate 6SRS was closed when the ip-flop circuit 9RH operated.

To briefly recapitulate,.the effect of a service request pulse from the line concentrator lup to this point is to operate theip-op circuit SHGT which stops the register counter 1000 and the transmission of vertical group pulses to the line concentrator. It also stops the transmission of reset pulses to the line concentrator as reset pulses, but sends them, if line 1L00 is one of the five lines being cyclically scanned, as vertical file pulses to the line concentrator. This is necessary since thesource 7PS does not provide a vertical file pulse for line 1L00 and the reset pulse functions to provide a scanning pulse therefor at the concentrator. The source 7PS will provide a reset pulse only if ythe vertical group is being scanned. Finally, circuit SHGT also blocks the random pulse supply to allow the service request -path to remain open.

When relay SHG operates, it places, byv closing contact IMSI-IG), the volt'battery 10B on one side of the windings of ve relays 10VFTO-4 which are connected respectively through the varistors 10ml-4 to the output terminals 2 of the stages 10VFRO-4 lin the counter 10VFR. When relay `SHG' operates, it also connects, at its Contact 11(-8HG), the vv Q20 volt battery: 11B to the twelve windings of the relays .'1'1VGTO-11 which are connected respectively through varistors 11-V0-,11 to the output terminals 2 of the stages 11VGRO-11. With the counters IOVFR Iand 11VGR stopped on the line location of the calling subscriber a --2V volt potential is on the other side of one of the relays 10VFTO-4 and one of the relays 11VGTO11 causing them to operate. The operation of one of the relays 10VFTO-4 and one of the relays 11VGTO-11 calls in central oce switching circuit 800 which includes markers and connectors-of the type described in the Patent y2,585,904 `which'issued to A. J. Busch on February 19, 1952, and lalsofas briey described in the above-identified application to A. E. Joel, Jr., et al. For example, Vif the call is initiated, from line 21u04, relays 10VFT4 and 11VGTO ,are operated to close ,contacts 8(10VFT4) and 'S(11VGTO) and provide indieating paths from battery SBS to circuit '800.

When one ofthe relays 10VFTO-4 operates it Ialso closes a path from terminal 6 of the source 7PS to the input terminal 1 of the Ailip-ilop circuit 9RL. With one of the relays 10VFTO-.4 operated, the corresponding verti cal le pulse from source 7PS passes through its contact 9(10VFTO-4) and the varistor 9V4 to set -the ip-op circuit 9RL. The terminals of varistor 9V4y are connected to ground through the resistors 9R10 and 9R11. If the line 2L04, for example, is the call initiating line, relay 10VFT4 is operated and the next vertical tile pulse 4, 10 milliseconds after the vertical le pulse, which initiated the service request, passes through the closed contact 9(10VFT4) to operate or set the flip-flop circuit 9RL.

If the circuit 9RL, -Which is similar to the circuit SHGT, remains in this condition it resets, as is hereinafter described, the circuit `SHGT to return the central oflice to normal.

During the time that the central oice control circuit '800 is being called in, the pulse 'source 7PS continues to supply the reset, vertical group and vertical le pulses. As described above, however, the only pulses that `are sent to the line concentrator are the vertical file pulses and when the vertical group 0 is being scanned, the reset pulse over the vertical le path. Every time the vertical le pulse lcorresponding to the calling subscriber is sent, which is once every 10 milliseconds, a service request pulse comes back to the central office and through the open gate 6SCR, the amplifier 9RLD1 and delay circuit 9RLD2 to the reset terminal 3 of the ip-op circuit 9RL. The circuit 9RL is set, as described above, by the vertical le pulse corresponding tothe calling line and is reset by the servicev request pulse, originating-at the concentrator from the same vertical le pulse, which is delayed by the circuit 9RLD2. If the subscriber abandons the call and the second service request pulse is not received the circuit 9RL opens the enabling gate 9RL1to allow the -Ynext timing tpulse from'the s'ource`7PS to-pass through and through the open inhibiting gate SRL, capacitor SC3 land 4the amplifier SHGTA to reset the flip-op circuit SHGT. The amplilier SHGTA may be similar to amplier 6VFL.

With the ip-op circuit SHGT reset it causes the release of the relay SHG which in turn releases the operated ones of the relays 10VFTO-4 and llVGTtl-ll and the demand to the central oce control circuit *800 is removed. When circuit SHGT is reset it also restores the various gates to their normal scanningcondition. The next'reset pulse from the ysource 7PS causes the counter circuit 109i) in the central oice and the counter circuit 500 in the line concentrator to return to normal and another line scan starting with line 2L00 is started. When.

ever scanning yis resumed, the line 2L00 is the rst line to be scanned.

The gate 6SRS, however, remains closed or inhibited so that the central ofce is insensitive `to service requests. Gate GSRS was originally closed when ip-op 9RH operated but an additional control potential was supplied thereto from the ilip-op circuit SRNS through the varistor 8D4. The flip-flop circuit SRNS remains set for a random interval under control of the random free-running generator SPG. If, for example, the interval between pulses from thev generator SPG is milliseconds, the flip-Hop circuit is reset anywhere from 0 to 115 milliseconds after the gate SRRN is opened. Gate SRRN is opened after the flip-opcircuit vSI-IGT and the llip-flop circuit 9RH reset. When circuit SHGI4 resets it opens gate 9RH1 to allow the next timing pulse to reset circuit 9RH to reopen gate SRRN. There is no synchronism between the pulse sequence in the scanning cycle and the free-running -generator SPG. The interval between pulses from generator SPG may be milliseconds, more than 120 milliseconds or less than 120 milliseconds.

If the interval is 120 milliseconds or more the system may not become sensitive within the next scan cycle and if the interval is too small, for example 2O milliseconds, the subscriber lines which are scanned towards the end of the scanning cycle are never the rst electively scanned lines. In the illustrative embodiment of the present invention, as described above, the interval between pulses is 115 milliseconds. The rst'eifectively scanned lines are those lines which are scanned immediately after the central office becomes sensitive to service requests. The central oice, as described above, becomes sensitive to service requests a random interval after scanning has been resumed which is when the gate GSRS is opened.

With the assurance however that there is a constant dial-tone request, the demand to the circuit S00 is sustained and the call proceedsin a normal manner. The successive detection of the service request pulses veries the continuance of the request since the service request pulse resets the circuit 9RL to disable the gate 9RL1so that the next timing pulse from source 7PS does not pass through to reset the circuit SHGT.

With a sustained demand to circuit 800, by the con* nection of battery SBS thereto through an operated one of the contacts 8(10VFTO-4) and through an operated one of the contacts 8(11VFTO-11), the circuit S00 functions to apply -2 volts to lead SLS to condition the central oiice control circuit for the transmission of set signals to the line concentrator; The 2 volts on lead SLS function to disable the gates SRL, 6CHO, 6VFS, 7VGS1 and 7R81 and to enable the gates 6LBT, 6VFT, 7M, 7VGT and 7RST. After readying these gates the circuit 800 controls the pulse source '7PS through lead SL4 to supply a reset pulse and the correct number of vertical le and vertical group pulses to set the counter circuit 50i) at the line concentrator to the identity of the calling line.

When -gate 6VFS is opened the vertical group pulses to the concentrator are stopped. When the flip-flop circuit 9RL is set it remains set since a service request pulse is not returned from the concentrator. When circuit 9RL sets it opens gate 9RL1 which allows the next timing pulse through to gate SRL. The gate RL, however, was opened by the switching circuits 800 so that the iiip-fiop circuit SHGT remains set. The circuit SHGT remains set until after the call has been serviced.

After the pulse source 7PS supplies the reset, vertical file and vertical group pulses it supplies a series of mark pulses to the concentrator to effect the connection of the calling line to one of the trunks 4T. The mark pulses are supplied through gate 7M, amplifier rIML, which is similar to amplifier GVFL, transformer 4T2 and the control pair 4CPI to the concentrator. The lower primary of transformer 4T5 is connected to the amplifier IMK which is similar to the amplifier IVF. The output terminal 2 of amplifier IMK is connected to the fiip-iiop circuit IM which is similar to the circuit SHGT described above. Circuit IM operates relay 3M which is connected to the output terminal 2 of circuit IM and also to battery SBI. When relay 3M operates, it connects battery SBI through its operated contact 3(3M) to the windings of relays 3F0-4 and SGO-11. The relays 31570-4 are connected respectively through varistors 3V0-4 to the output terminals 2 of stages 3VFO-4 in counter SVP and the relays 3G0-11 are connected respectively through varistors SVO-II to the output terminals 2 of stages SVGO1I in counter SVG. Since as described above the pulse source '7PS supplies a number of vertical group and vertical file pulses which indicate the identity of the calling line to the concentrator, the counters SVP and SVG are set in accordance therewith. If, for example, the stage lVF-t and the stage 5VGO are set, the relays 31:4 and 5G0 operate when contact 3(3M) closes. l

With one of the relays 3130-4 operated and one of the relays 5G0-11 operated the -65 volt source 5B is connected to the winding of one of a plurality of relays 4C0. The relay iC0 shown in Fig. 4 is associated with the line 2504i and has the battery 5B connected thereto when the contacts 5(3F0) and 5(5G0)4 are operated. There is at least one relay C0 for each of the subscriber lines 250G-59 for providing a connection therefrom to one of the trunks 4T. In the line concentrator described in the above-identified disclosure by Ioel-Krorn-Posin there are six relays 4C0 for each line, providing possible connections to six out of ten trunks that connect the line j' the winding of the relay 4C0 to the cathode of tube CD causes the tube LCD to ionize and establish a conductive path through the relay 4C0.

When the relay ICO operates it closes the four contacts 4(4C0)14. The contacts 4(4C0)I-2 establish a connection between the line 2L0=1l and the trunk 4T to the central ofiice. The third contact 4(4C0)3 makes a connection from point S in the line scanner 2LS04 through the inductor iBTL to the 20 volt battery 4B5. The connection of the battery IBS to point S in the line scanner 210804 changes the potential at point S to volts so that the line 21.04 will not indicate a service request when line scanning is resumed. The -20 volts at point S reverse-biases the varistor 2S so that service request pulses are not provided to the amplifier ISR. When scanning is resumed, as is hereinafter described, a scanning pulse applied to the line scanner 21,04 passes from point S through the closed contact tOi-Cm3, varistor 4BTI and amplifier ILB, which is similar to amplifier GVFL, through transformer Tdi and the control pair 4CPO to the central office. The input terminal 1 of amplifier ILB is connected tobattery 1134 through resistor 1R9 shunted by capacitor ICQ. The control pair 4CPO is connected through transformer 4T1, the amplifier 6LBL which is similar to the amplifier IVF described above, the open enabling gate 6LBT, and lead SLI to the circuit 800. In this manner when line scanning is resumed the scanning pulses to lines which are busy, that is, connected to a trunk 4T, are converted by the associated ones of the line scanning units 2LS00-59 to line busy pulses and supplied to the central ofiice. The line scanning units 2LS00-59 therefore function not only to determine the calling condition of a line but also to supply a line busy indication thereof to the central ofiice. A separate path, not shown, may be provided from the amplifier 6LBL to the circuits 800 for the reception of these pulses.

When relay 4C0 operates it also functions to change the bias of a diode 4MV from +30 volts to allow the rest of the mark pulses from the central office to pass through. The diode 4MV was reversed-biased by the battery 4136 which is connected thereto through the resistor 4L1, varistor 4RV and resistor 4BR. The other terminal of varistor 4MV is connected to ground through the resistor 4MR and to the output terminal 2 of the amplifier IMK through the capacitor 4MC, When relay C0 operates it extends the connection from the volt battery 5B through the operated contact 4(4C0)4, the varistor (SRV and resistor 4L1 to the battery 4B6 locking relay 4C0 operated. The current through resistor 4L1 causes the potential at varistor 4MV to decrease and allow the mark pulses through. With the varistor 4MV in this condition the succeeding marking pulses from the central ofiice through the amplifier IMK are supplied through the capacitor 4MC, varistor 4MV and capacitor CTI to the input terminal 1 of the line busy amplifier ILB. In this manner the succeeding marking pulses are routed back to the central office through the amplifier ILB as line busy pulses to indicate that the crosspoint relay 4C0 has operated.

When such a series of line busy pulses are received at the circuits 800 it removes the readying potential from lead SLS and initiatesthe operation of the source 7PS to supply a reset pulse to the line concentrator and to circuit 1000. Both circuits 500 and 1000 are reset and the normal scanning cycle is resumed.

When gate SRL is opened by the switching circuits 800 the next timing pulse from terminal 7 of source 7PS passes through gates 9RL1 and SRL, and amplifier SHGTA to reset the circuit SHGT.

When the circuit SHGT releases it releases relay SHG; closes gates 6SRC and 6VF; opens gates 9RRG, 7VGS2 and 7R82; and removes a control potential from gate SRRN which remains closed however under control of the circuit 9RH. After gate 9RRG is opened, the reset pulse from terminal 3 of source 7PS is supplied through the gate 9RRG and amplifier 9RR to the reset terminal 3 of circuit 9RH. The amplifier QRR is also connected through varistor 9V8 to the reset terminal 3 of the flip-flop circuit 9RL which is therefore also reset. When relay SHG releases it opens the operating paths for relays 10VFT4 and 11VGTO to open the operating path for circuit 9RL also the starting path for the switching circuits 800.

When the circuit 9RH is reset it opens gates 9VGR and 9VFR to also the vertical group and vertical-file pulses through to the counter 1000; opens the gate SRRN; and closes the gate 9RNS. Gate 9RNS provided a passage for timing pulses to set the flip-flop circuit SRNS as described above and when circuit SRNS Was set it closed gate 6SRS to make the central office insensitive to service request pulszes from the concentrator. The gate 6SRS is in the input; path to the flip-flop circuit SHGT. As long .as gate 6SRS is open, the circuit SHGT cannot be set to 

